`include "simpleCPU.v"
`timescale 1ps/1ps

module testCPU;

reg clk, reset;
initial clk = 0;
always #5 clk = ~clk;

initial reset = 0;

simpleCPU CPU(clk, reset);

initial
begin
    $readmemh("./RomData/instrRom.dat", CPU.InstructionMemory.units);
    $readmemh("./RomData/dataRom.dat", CPU.dataMemory.units);
end

initial
begin
    #5 reset = 1;
    #2 reset = 0;
    #50 $stop;
end

always @(CPU.instruction)
    if(CPU.instruction == 32'h00000000)
        $stop;

initial
begin
    $dumpfile("../bin/cpu.lxt");
    $dumpvars;
end




endmodule